`timescale 1ns / 1ps
// module name: tb_memory
// author: yangtao2019
// date: 2021.07.11

module tb_memory;

    // parametrs
    parameter ADDR_LEN = 7;
    parameter CAPACITY = (2<<ADDR_LEN)*32;

    // inputs
    reg clk;
    reg read;
    reg write;
    reg [ADDR_LEN-1:0] addr;
    reg[31:0] write_data;

    // output
    wire [31:0] read_data;

    memory inst_mem( 
                    .clk(clk),
                    .read(read),
                    .write(write),
                    .addr(addr),
                    .read_data(read_data),
                    .write_data(write_data)
                );

    // memory data_mem( 
    //                 .clk(clk),
    //                 .read(read),
    //                 .write(write),
    //                 .addr(addr),
    //                 .read_data(read_data),
    //                 .write_data(write_data)
    //             );

    initial begin
        clk = 0;
        read = 0;
        write = 0;
    end

    initial begin
        forever #20 clk = ~clk;
    end

    initial begin
        #20
        write_data = 32'b1;
        #30
        write = 1;
        addr = 7'h12;
        #30
        write = 0;
        read = 1;
        addr = 7'h34;
        #100
        write_data = 32'b0110;
        #30
        read = 0;
        write = 1;
        addr = 7'h12;
        #50
        write_data = 32'b0110;
        #30
        read = 1;
        write = 0;
        addr = 7'h12;
        #100
        read = 0;
        write = 0;
    end 

endmodule

